By Himanshu Bhatnagar
Advanced ASIC Chip Synthesis: utilizing Synopsys® Design Compiler® actual Compiler® and PrimeTime®, Second Edition describes the complex thoughts and methods used in the direction of ASIC chip synthesis, actual synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. moreover, the full ASIC layout move technique specified for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.
The emphasis of this ebook is on real-time software of Synopsys instruments, used to wrestle quite a few difficulties visible at VDSM geometries. Readers might be uncovered to a good layout technique for dealing with complicated, sub-micron ASIC designs. value is put on HDL coding types, synthesis and optimization, dynamic simulation, formal verification, DFT test insertion, hyperlinks to structure, actual synthesis, and static timing research. At each one step, difficulties similar to every part of the layout movement are pointed out, with strategies and work-around defined intimately. furthermore, an important concerns comparable to structure, along with clock tree synthesis and back-end integration (links to structure) also are mentioned at size. in addition, the booklet includes in-depth discussions at the foundation of Synopsys expertise libraries and HDL coding types, specified in the direction of optimum synthesis resolution.
aim audiences for this publication are working towards ASIC layout engineers and masters point scholars project complicated VLSI classes on ASIC chip layout and DFT strategies.
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Functional gate-level simulation of the design with post-layout timing (if desired). 14. Tape out after LVS and DRC verification. 1 Chapter 1 Physical Synthesis Traditionally synthesis methods are based on using the wire-load models. The basic nature of the wire-load models is such that they are fanout based. In other words, the delay computation of cells is performed based on the number of fanouts a cell drives. 35um), it is not suitable for smaller geometries. The resistance of wires is dominating the cell delays causing the fanout based delay computation to be unreliable and totally unpredictable.
To remove these violations, you must re-synthesize/optimize the design with the dont_touch attribute removed from the sub-blocks. DFT scan insertion at the top-level is another reason for removing the dont_touch attribute from the sub-blocks. This is due to the fact that the DFT scan insertion cannot be implemented at the top-level, if the sub-blocks contain the dont_touch attribute. The following script exemplifies this process by performing initial synthesis with scan enabled, before recompiling (compile –only_design_rule) the design with dont_touch attribute removed from all the sub-blocks.
Similar to synthesis, static timing analysis is also an iterative process. It is closely linked with the placement and routing of the chip. This operation is ASIC DESIGN METHODOLOGY 11 usually performed a number of times until the timing requirements are satisfied. 6 Placement, Routing and Verification As the name suggests, the layout tool performs the placement and routing. There are a number of methods in which this step could be performed. However, only issues related to synthesis are discussed in this section.